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TestBench
- 怎样写testbench 本文的实际编程环境:ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_log
vga
- Verilog实现的VGA程序,用ISE打开工程文件即可-Verilog implementation VGA program, open the project file with the ISE can be
seven_seg
- Verilog, 7segment, ISE
adc2
- ADC control in VHDL language. Spartan 3E starter pack ISE 10.1
ml505_mig_design
- Xilinx开发板ML505的DDRII示例程序,使用Verilog,调用MIG,编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
IFFT
- 这是关于傅里叶反变换的一个完整的ISE的工程..使用verilog语言-This is on the Fourier transform of a complete anti-ISE project using the verilog language ..
SERDES
- 基于Verilog的串并转换器的设计与实现,采用两种不同的方案来实现串并和并串转换的功能,并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE softwa
Realization_of_FPGA_for_LDPC_encoding
- 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码,它的直接编码运算量较大,通常具有码长的二次方复杂度.为此,利用有效的校验矩阵,来降低编码的复杂度,同时研究利用大规模集成电路实现LDPC码的编码.在ISE 8.2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程,为LDPC码的硬件实现和实际应用提供了依据-Abstract:Low.density parity·check code(LDPC code)is a kind of linear eror
DCM_12M_1M
- xilinx下DCM输出12Mhz和1Mhz-Verilog DCM xilinx ISE
IS61WV51216BLL
- 备注:使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1,硬件:高教仪EXCD-1FPGA电路板。FPGA信号:spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写,通过串口发送到上位机上,使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
rax2
- rax2 fft implation the fft in verilog instance and in ise of xilinx it show how to istance fft core and the port used
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
ise11tut
- Verilog语言开发环境ISE例程,适合于初学者-ISE Verilog language development environment routines, suitable for beginners
wtut_ver
- Verilog语言开发环境ISE例程,适合于初学者-ISE Verilog language development environment routines, suitable for beginners
wtut_vhd
- Verilog语言开发环境ISE的一些例程,适合于初学者-ISE Verilog language development environment for a number of routines, suitable for beginners
xiayuwen
- 本程序是夏宇闻老师的verilog数字系统设计教程中的E2PROM完整程序文件,包括信号产生模块,E2PROM读写模块,E2PROM模拟模块,并且在ISE上运行成功,测试正确,modelsim仿真成功-This program is the Xia Yu Wen digital system design tutorial E2PROM complete file, including the signal generation module, E2PROM reader module, E2P
synth_fft
- fftprocessing can complete 256 pointsFFT.-Hardware Descr iption Language(HDL)is an advanced electronic designmethod.After HDL was put into use,it has draw great attention and gained popularity.The design used Verilog HDL and Schematic for entry tools
ddr
- 基于FPGA的ddr控制器的设计与实现,verilog,ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
fifo
- verilog实现fifo,ise中仿真,chipscope调试-verilog achieve fifo, ise in the simulation, chipscope debugging
HDB3
- 在ISE软件环境下,用Verilog HDL语言实现通信中的HDB3码的编码和译码,并有仿真波形。-In the ISE software environment, using Verilog HDL language for communication in the HDB3 code encoding and decoding, and a simulation waveform.